DDR stands for double data rate. Physical DDR interfaces (PHYs) require accurate timing when various signals, such as clock, command, address, and data signals are each launched. Incoming signals are also delayed to be captured. In some existing approaches, delay lines are used to delay such signals, but need to be compensated against manufacturing process, supply voltage, and temperature (PVT) variations.
In high speed operations of the DDR PHYs, such as operations in the range of Giga-bits per second, delay locked loops are used to calibrate the delay lines. Different ways of calibration are used. For example, calibration is performed once when the circuit is initialized or is performed continuously during operations of the circuits when the signals drift during circuit operations. Further, when semiconductor chips that have DDR interfaces and related circuits manufactured on a printed circuit board, board artifacts, such as trace length mismatches, need to be compensated.
Like reference symbols in the various drawings indicate like elements.